Top Semiconductor Manufacturers and Foundries Ranked by Revenue and Capacity 2026

Rankings are usually a way of tidying a market. This year they are a way of measuring how untidy it has become. The 2025 numbers are in — Gartner puts worldwide semiconductor revenue at approximately US$796 billion, up around 21% — and the 2026 revisions that followed are unlike anything in the industry's modern record: WSTS-aligned projections now sit between US$1.51 trillion and US$1.66 trillion, implying growth of 90–108% in a single year, led by memory at a projected 250–300%.

Numbers that steep deserve suspicion, and the closing section of this feature applies some. The ranking itself, though, is not in dispute. Ten companies produce the overwhelming majority of the world's third-party wafers. One of them produces most of those. And the capacity that matters — leading-edge logic, high-bandwidth memory, advanced packaging — is concentrated in remarkably few hands, in remarkably few places.

What follows ranks the foundries and the integrated device manufacturers by 2025 full-year revenue and early-2026 run rate, then works through the capacity estimates the revenue tables imply but do not show. The procurement workflow — evaluation criteria, contract checkpoints, total cost of ownership — lives in the companion buyer's guide. This piece is about the structure of the market itself.

How to Read a Semiconductor Ranking in 2026

A ranking is only as honest as its categories, and this industry runs on three. Integrated device manufacturers — Samsung, SK Hynix, Micron, Intel — design and fabricate their own chips, often with memory or specialty strengths. Foundries, pure-play or captive, manufacture for third parties; TSMC, Samsung Foundry, SMIC, UMC and GlobalFoundries lead that trade. Fabless designers — NVIDIA, AMD, Broadcom, Qualcomm, Apple — top the vendor charts while owning no factories at all, which is why pure-play foundries dominate advanced-node production on their behalf.

The tables that follow rank by two different things, deliberately. Revenue is audited, comparable and slightly backward-looking. Capacity — wafer starts per month, node mix, packaging slots — is what a buyer actually contracts for, and its exact figures are closely held; what circulates are estimates, utilisation disclosures and the occasional filing. This feature draws on 2025 full-year results, early-2026 quarterly data and industry forecasts, and it prioritises semiconductor-specific manufacturing activity over corporate totals. Where a number is an estimate, it is labelled as one.

One more distinction earns its place before the tables. Leading-edge means the nodes at or below 5 nanometres — the N3, N2 and 18A class — where AI accelerators and flagship processors live and where constraint is acute. Mature and specialty nodes, 28 nanometres and older, make the power-management ICs, analog parts, microcontrollers and sensors that fill the rest of every bill of materials. The two markets share a name and almost nothing else: different customers, different economics, different geography, and — in 2026 — very different availability.

The Foundry Scoreboard: Seven of Every Ten Dollars Go to One Company

The top ten foundries billed a combined US$169.5 billion in 2025 — a record, up 26.3% on the year — and TSMC collected 69.9 cents of every one of those dollars. TrendForce's full-year tally, in the table below, is worth reading slowly. The gap between first and second place is not a gap; it is a different industry. TSMC's US$122.5 billion is nearly ten times Samsung Foundry's US$12.6 billion, and TSMC grew 36.1% while Samsung contracted 3.9% in the strongest foundry market ever recorded.

The quarters since have widened the spread. Q4 2025 closed with TSMC at US$33.7 billion and a 70.4% share, against Samsung's US$3.4 billion and 7.1%. In the first quarter of 2026, TSMC's revenue reached roughly US$35.9 billion and its share moved past 72%. The top ten together grew 32% year on year to about US$48 billion that quarter — and most of the increment belonged to one company.

Beneath the two leaders, the table sorts into deliberate strategies rather than failed ones. SMIC, at US$9.3 billion and 16.2% growth, and HuaHong, at US$4.5 billion and 25.2%, are compounding on Chinese localisation demand while remaining fenced off from EUV tooling. UMC and GlobalFoundries — US$7.6 billion and US$6.8 billion — run the specialty and mature-node franchise: slower growth, defensible sockets, long design lifetimes. Tower, Vanguard, Nexchip and PSMC each cleared roughly US$1.4–1.6 billion. Nobody in the bottom half of this table is trying to catch TSMC. The economics stopped permitting the attempt years ago.

One definitional note keeps the table honest. TrendForce counts pure-play and captive foundry activity together — Samsung Foundry is a division selling manufacturing to outsiders while its parent remains its largest customer — so the figures above are foundry revenue, not corporate totals. The ranking throughout this feature prioritises semiconductor-specific manufacturing. The design houses appear later, where they belong.

The share-expansion mechanics are worth naming, because they compound. Each node transition raises the price of a leading-edge wafer, and TSMC currently ramps those transitions alone at scale — so its revenue share can climb even in quarters when its wafer volume barely moves. Competitors on flat mature-node pricing cannot arithmetically keep pace. Unless Samsung's yields or Intel's 18A change the denominator, the 72.3% recorded in the first quarter of 2026 reads less like a peak than a waypoint.

Who Actually Controls Leading-Edge Capacity in 2026?

Below 7 nanometres, the market is one company, a determined second, and a policy project. Wafer-start capacity is the number everyone wants and nobody publishes, but the available estimates converge: TSMC's network — Taiwan at the core, with Arizona, Kumamoto and a European site attached — runs on the order of 1.6 million 12-inch-equivalent wafers per month, a dominant share of pure-play foundry capacity. Advanced nodes are where that capacity earns. Processes at 7 nanometres and below contributed more than 70% of TSMC's wafer revenue in early 2026, by some readings 77%.

Concentration sharpens at the edge itself. Late-2025 projections put TSMC at roughly 69% of advanced-process capacity among the top three manufacturers, Samsung near 21% and Intel around 10%. Those three numbers are the entire leading-edge market. N3 and N2 are fully booked. CoWoS — the chip-on-wafer-on-substrate packaging that every serious AI accelerator now routes through — is sold out through much of 2026. A customer arriving today for leading-edge volume is negotiating for 2027.

Set the revenue table against the capacity estimates and the industry's pricing structure becomes visible. TSMC's roughly 1.6 million monthly wafers sit well under a fifth of the nine million 300 mm wafer starts the world was running by early 2026, memory fabs included — yet the company books seven of every ten pure-play foundry dollars. Value density does the work. A leading-edge logic wafer bills at a multiple of a mature-node one, and TSMC sells most of the leading edge.

The rest of the world's capacity is real but different in kind. Most of the global base runs mature and specialty processes — 28 nanometres and older — at SMIC, UMC, GlobalFoundries, HuaHong and the smaller Taiwanese and Japanese houses. SMIC fabricates 7-nanometre-class silicon on deep-ultraviolet multi-patterning, an expensive workaround that export controls have made permanent. At the trailing edge, 8-inch capacity is quietly shrinking as TSMC and Samsung wind it down, tightening supply of the power-management and analog parts AI servers consume in volume. Mature does not mean available.

Samsung's position deserves precision. It is the only manufacturer shipping gate-all-around transistors at scale — it adopted GAA at 3 nanometres before TSMC — and its 2-nanometre-class line is the only credible second source for leading-edge logic. What it has not solved is yield and utilisation, which is why its foundry revenue fell in a record market. Intel's 18A process, ramping in Arizona with backside power delivery, anchors a foundry offer that Washington's reported equity stake now underwrites; its scale, for now, is the 10% figure above.

Advanced Packaging: The Constraint Nobody Ranks

The binding constraint on AI silicon in 2026 is not always the wafer; often it is the package around it. A modern accelerator is an assembly: logic dies and stacks of high-bandwidth memory mounted side by side on a silicon interposer, the whole arrangement bonded to a substrate. TSMC's CoWoS line is where most of that assembly happens for the chips that matter, and CoWoS has been sold out through much of 2026. A booked N2 wafer with no packaging slot behind it is inventory, not product.

This is why packaging now moves markets that wafer capacity alone cannot explain. Interposer area, substrate supply and HBM stack availability each gate final output independently, and expanding any of them is slow, exacting work — closer to building a fab than to adding a production shift. The assembly-and-test tier below the headline names — ASE, UTAC, STATS ChipPAC and their peers — is absorbing demand that the advanced lines cannot take, and the sourcing teams that treat packaging as a line item rather than a constraint are the ones that discover it last.

The practical read for 2026 planning: monitor packaging allocation with the same discipline applied to wafer allocation. Lead times at the leading edge already exceed a year for N2 and N3 volume; the packaging queue can add to that or, managed early, run inside it. Nothing in the current capacity data suggests the constraint clears this year.

The IDM Ledger: Memory Rewrote the Rankings

The integrated device manufacturer table is now a memory table with Intel attached. Gartner's 2025 semiconductor revenue ranking places NVIDIA — a company that fabricates nothing — at the top on US$125.7 billion and a 15.8% share, which says as much about the industry's structure as any capacity chart. The names below it are the manufacturers, and three of the four are memory businesses.

Then 2026 happened to the memory makers. SK Hynix reported second-quarter revenue of roughly US$56 billion, up 257% year on year, on mass shipments of HBM4 — a single quarter within sight of its entire 2025 total. Micron posted about US$41.5 billion in one reported fiscal quarter. Samsung's semiconductor division is compounding on HBM and a recovering foundry book. Intel, holding fourth on US$47.9 billion, is the outlier whose story is process rather than product: 18A and the foundry build-out carry more weight than any single chip line.

The mechanism matters more than the print. HBM is not made alongside conventional DRAM; it is made instead of it. Every wafer reallocated to HBM stacks removes commodity bits from the market, and the reallocation has already tightened DRAM and NAND supply. The 250–300% memory growth inside the 2026 projections is a price story as much as a volume story — which also makes it the least stable line in the forecast.

Samsung is the table's structural oddity: the only company ranked near the top of both ledgers, second among IDMs on US$72.5 billion while running the second-largest foundry. That breadth cuts both ways. Memory strength funds the foundry's long yield campaign, and the foundry gives Samsung a call on the AI logic boom its memory rivals lack — but it also means Samsung competes with its own foundry customers in ways TSMC never has to, a conflict every prospective client prices in.

For the fabless tier, this ledger is the mirror checked nightly. NVIDIA, Qualcomm, Broadcom, AMD and Apple hold their positions precisely because they own no fabs — and every one of them is exposed to the same two suppliers for advanced wafers and the same three for memory. The industry's revenue has never been spread across more logos, and its production has never depended on fewer factories.

Where Is the 2026 CapEx Actually Going?

The capital budgets being written now decide the 2027 rankings, and they are the largest the industry has carried. TSMC raised its 2026 guidance to US$60–64 billion, a record for any chipmaker. The destinations are telling. Arizona's first module is producing 4-nanometre wafers at yield parity with Taiwan — the qualifier that mattered — with major further expansion planned. JASM in Kumamoto is running. A European site is in build. The centre of gravity stays in Taiwan, where N2 ramps, but the geographic hedge is finally measured in installed tools rather than announcements.

Samsung is building Taylor, Texas, alongside Pyeongtaek and Hwaseong. Intel is adding Arizona capacity under its 18A ramp, with CHIPS Act incentives and the reported federal equity position behind it. Equipment and construction spending across the industry remains elevated. The arithmetic stays uncomfortable even so: leading-edge output growth lags demand through at least 2027, because a fab funded today is wafers in 2028. New capacity in the United States, Japan, Europe and Korea will diversify supply gradually — emphasis on gradually.

The demand side gives that spending its floor. Utilisation across leading-edge and advanced packaging is effectively full, memory pricing power is expected to hold through the year, and the mature-node segment — long the industry's slack capacity — is tightening selectively as AI power-management volumes climb. Elevated capex against elevated utilisation is not a market loosening. It is a market queuing.

For buyers, the CapEx map conceals the harder constraint: switching cost. A design taped out on one foundry's process does not move. Porting to a second source means new process design kits, new masks at eight-figure cost, re-characterisation, and requalification measured in quarters. The gate-all-around transition at 2 nanometres deepens the moat, because design rules diverge further between TSMC, Samsung and Intel with each node. Dual-sourcing is a decision made at architecture time, not at negotiation time. That — more than any line in these tables — is what vendor lock-in means in 2026.

Singapore's Position: The Profitable Middle of the Market

Singapore fabricates roughly one in ten of the world's chips without running a single leading-edge logic line. Sector output is about S$133 billion a year, near 7% of GDP, and the country produces around 20% of global semiconductor equipment. More than 35,000 people work in the industry. Over S$30 billion in new investment arrived between 2022 and 2025, and the 2026 pipeline is larger still.

The current build-out extends the base rather than chasing the frontier. Micron broke ground in January on a US$24 billion NAND fab — Singapore's first double-storey wafer plant, with production scheduled from the second half of 2028; the full analysis of that project is on this desk. UMC's new fab reaches volume production this year on 22-nanometre process, the most advanced in the country, at up to US$5 billion for phase one and 30,000 wafers a month — taking its Singapore capacity past a million wafers annually. GlobalFoundries, SSMC and VSMC run alongside; UTAC, ASE and STATS ChipPAC anchor the assembly-and-test layer.

Read against the global ranking, Singapore's slice is the part of the market where allocation still functions. The leading edge is spoken for years out; mature, specialty and memory capacity is where second sources, automotive-grade silicon and power management actually get made — and that is the capacity Singapore is adding. Buyers building regional supply chains can work from the directory's semiconductor category or the current Singapore semiconductor shortlist.

The equipment figure deserves a second look, because it ties Singapore to every fab on this page. Roughly a fifth of the machines that build and run the world's cleanrooms are made in or shipped through Singapore's manufacturing base. When TSMC equips Arizona, when Samsung fits out Taylor, when Micron tools its own fab up the road — a measurable share of that record global capex lands as Singapore export orders. The country is long the build-out itself, not just its own fabs.

What Should Boards Take From These Tables?

The ranking reduces to four sourcing facts that will not change before 2027.

• Leading-edge logic is a TSMC negotiation. Samsung is the only secondary, and N2/N3 lead times can exceed a year. Where the accelerator roadmap matters, capacity reservations and prepayment have replaced spot ordering.
• HBM is a three-supplier market. SK Hynix leads; Samsung and Micron follow. Reallocation toward HBM keeps conventional DRAM and NAND tight, so memory contracts signed in 2026 price in scarcity. Treat that assumption as reviewable, not permanent.
• Mature nodes are the only real diversification. UMC, GlobalFoundries, Tower, VIS and the Chinese foundries offer genuine geographic spread across Singapore, the United States, Israel and Japan — though AI power-management demand is lifting utilisation there too.
• Geopolitics is now a design input. Taiwan concentration, CHIPS Act incentives and China's localisation push shape sourcing before the RFQ stage. Multi-sourcing gets designed in at tape-out, or it does not happen.

A caution on the forecasts, as promised. Projections of 90–108% industry growth lean on memory pricing that is itself a function of shortage; the industry has built capacity into the top of a cycle before, and these figures will move as audits land. The concentration numbers need no such caveat. They are results, not predictions.

One figure frames 2026 better than any projection. TSMC's capital budget for the year — US$60 billion to US$64 billion — exceeds the combined 2025 revenue of every other foundry in the top ten.