AI Chip Manufacturers in 2026: Architecture Wars, Inference Economics and the Southeast Asia Build-Out

Two years ago the AI accelerator market was a queue outside one company's door. In 2026 it is a genuine field: two merchant GPU vendors shipping at scale, four hyperscalers deploying their own silicon in volume, two enablers quietly building most of that custom silicon, and a set of specialists that make money answering one question — what does a token cost to produce?

This analysis is written for the people who have to commit capital against that question: infrastructure architects sizing clusters, procurement teams negotiating allocation, and boards weighing a build in Singapore against one across the causeway. The companion pieces cover the foundry and memory ranking beneath these chips and the Singapore data-centre build-out they land in.

Executive Summary: An 80% Market That No Longer Behaves Like One

The bottom line first: NVIDIA still sets the industry's clock, but 2026 is the first year a large buyer can assemble a credible AI stack without it. Analyst estimates put NVIDIA's share of AI-accelerator revenue at roughly three-quarters or more through the first half of 2026, down from near-total dominance two years earlier, in a market widely projected to pass US$600 billion annually by 2033. The erosion is not coming from a rival GPU. It is coming from customers becoming manufacturers.

The growth-rate gap tells the story more honestly than the share number. Industry trackers project custom ASIC shipments to grow about 44.6% in 2026 — nearly triple the rate of merchant GPUs — as Google, Amazon, Microsoft and Meta scale first-party silicon across their fleets. None of those chips is sold on the open market, so the share they take never shows up in a competitor's revenue line. It shows up as NVIDIA orders that were never placed.

The second structural shift is the workload itself. Inference overtook training as the industry's growth driver in 2026, and the two reward different silicon: training pays for raw throughput, memory bandwidth and interconnect; inference pays for cost per token, latency and watts. Nearly every new entrant — Qualcomm's AI200, Groq's LPU, Etched's Sohu, Cerebras at the high end — is aimed at inference economics, because that is where volume is compounding and where NVIDIA's system-level moat matters least.

None of this reads as decline in NVIDIA's results, and buyers should not confuse diversification with displacement. The hyperscalers deploying custom silicon continue to buy NVIDIA in enormous volume, using their own chips to cover predictable internal workloads and to discipline pricing on the rest. What has changed is the negotiating table. In 2024 there was one seat on the supply side. In 2026 there are, depending on the workload, as many as six.

Architecture Deep Dive: Three Ways to Build an AI Chip

Strip away the branding and the 2026 architecture war reduces to three bets about memory: stacked HBM at maximum bandwidth, stacked HBM at maximum fleet scale, or no external memory at all. GPUs take the first bet, hyperscaler ASICs the second, and the spatial accelerators — wafer-scale engines and SRAM-first designs — the third. Almost every specification that matters flows from that choice.

NVIDIA's shipping volume platform is Blackwell. The B200 pairs two reticle-limit dies into one 208-billion-transistor GPU with 192 GB of HBM3e feeding roughly 8 TB/s of bandwidth, and the GB200 NVL72 rack lashes 72 Blackwell GPUs — a higher-clocked variant of the B200, at roughly 5 PFLOPS dense FP8 each — to 36 Grace CPUs over fifth-generation NVLink at 1.8 TB/s per GPU: 130 TB/s of aggregate fabric that lets the rack behave as one very large accelerator with 13.4 TB of pooled HBM3e and about 360 PFLOPS of dense FP8. Its successor Rubin, entering volume in the second half of 2026 on TSMC 3-nanometre silicon, moves to 288 GB of HBM4 at up to 22 TB/s per GPU, with an NVL72 configuration holding 20.7 TB. The point of the architecture is the fabric: competitors must beat not a chip but a rack.

AMD's counter is memory capacity per device. The Instinct MI355X carries 288 GB of HBM3e at 8 TB/s — half again more memory than a B200 — and its CDNA 4 compute is competitive at roughly 5 PFLOPS of dense FP8, which lets larger models fit on fewer GPUs and cuts the interconnect tax that multi-node serving pays. The 2026 MI450 generation extends the bet to 432 GB of HBM4 at up to 23.3 TB/s, with the Helios rack holding 31 TB. ROCm has matured from liability to workable: hyperscalers now run production workloads on it, which is precisely what makes AMD useful as a second source.

Google's TPU is the systolic-array alternative, now seven generations deep and the only custom ASIC outsiders can rent at scale. Trillium, the sixth generation, doubled memory and bandwidth over its predecessor and delivered 4.7 times its peak compute; Ironwood, the seventh, reached general availability in April 2026 with 4,614 FP8 TFLOPS per chip, 192 GB of HBM3e at 7.37 TB/s, and pods that scale to 9,216 chips — 42.5 FP8 exaflops behind optical circuit switches. Amazon's Trainium takes the same fleet-first logic down-market on cost, a story the TCO section takes up below.

The spatial accelerators refuse the HBM bet entirely. Cerebras builds a four-trillion-transistor processor across a whole wafer — the WSE-3 — holding 44 GB of SRAM on-die at petabytes per second of internal bandwidth, and serves large open models at more than 2,100 tokens per second; it listed on Nasdaq in May 2026, raising US$5.55 billion. Groq's LPU keeps 230 MB of SRAM per chip with deterministic, compiler-scheduled execution and scales by adding chips rather than widening memory, a bet on cheap, fast token generation that has drawn heavy investor backing. Etched's Sohu hard-wires the transformer itself: an eight-chip server claims more than 500,000 tokens per second on a 70-billion-parameter model, against roughly 23,000 for a previous-generation eight-GPU system — a bet that pays only for as long as the transformer endures.

How Does HBM3e Memory Bandwidth Impact Long-Term Inference TCO?

Bandwidth, not compute, is the number that compounds into an inference bill. Generating a token requires streaming the model's active weights through the chip, so decode throughput is bounded by memory bandwidth long before the FLOPS run out; utilisation of the arithmetic units in bandwidth-bound serving commonly sits far below what any datasheet advertises. That is why a B200's 8 TB/s matters more to a serving fleet than its teraflops, why AMD sells memory capacity as economics rather than convenience, and why SRAM-first designs post token rates that HBM parts cannot reach.

It is also why the HBM4 transition is the real generational event of 2026–27. HBM4 doubles the per-stack interface width to 2,048 bits, which is how Rubin reaches 22 TB/s and the MI450 23.3 TB/s, and it is supplied by exactly three companies — SK Hynix, Samsung and Micron — whose advanced capacity is effectively pre-sold. High-bandwidth memory is now among the largest single line items in an accelerator's bill of materials. When a CFO asks why the chips are expensive, the honest answer is that the memory is.

Can Anything Break the CUDA Lock-In?

Not quickly, and not at the frontier — but the perimeter is shrinking. CUDA's advantage is nearly two decades of libraries, tooling and trained engineers; a rival can match NVIDIA's silicon and still lose the sale because porting, revalidation and retraining cost more than the hardware saves. Three forces are eroding the edge at the margins. ROCm now carries production workloads at hyperscalers; PyTorch and the Triton compiler abstract kernel authorship away from any one vendor's toolchain; and the hyperscalers sidestep the fight entirely, because a customer running on TPUs through Google Cloud or Trainium through AWS never touches CUDA at all.

The honest reading for an enterprise: frontier-scale training remains a CUDA market, inference is increasingly contestable, and the switching cost is largest for teams that write custom kernels rather than consume frameworks. Price the lock-in explicitly. It is a real cost, but it is no longer an unbounded one.

Financial TCO: What a Token Actually Costs

Sticker price is the least informative number in an accelerator purchase; power, utilisation and memory decide what a deployment actually costs. The table below compresses the field to the figures a procurement conversation starts from. Prices are estimates — merchant silicon is negotiated bilaterally, and hyperscaler chips are never sold at all, only rented as instances.

Read the table with its caveats attached. Peak figures are vendor-quoted dense FP8 except where noted, and no production workload runs at peak. The rack row is the honest unit of comparison for NVIDIA, because nobody deploys one B200; the NVL72 draws on the order of 120–130 kW, which makes liquid cooling mandatory and rules out most legacy data halls built for 8–15 kW racks. Retrofit cost belongs in the chip comparison, even though it never appears on a chip datasheet.

Why Does Model FLOPs Utilization Decide the Real Price of Compute?

Model FLOPs utilisation — the share of a chip's theoretical arithmetic a workload actually sustains — is the multiplier most TCO models omit. Well-run large training jobs typically sustain MFU in the mid-30s to mid-40s percent; a poorly parallelised one can sit far lower while burning identical power and rental hours. The arithmetic is unforgiving: a US$40,000 GPU at 40% MFU delivers cheaper useful compute than a US$25,000 alternative at 22%, and a cloud instance at twice the hourly rate can still win on cost per trained token if its fabric keeps utilisation high. Benchmark on your own model and traffic before trusting any per-hour price, because the quoted rate measures occupancy, not output.

Cloud pricing itself has split into two markets. Commodity H100 capacity that rented above US$8 per GPU-hour in 2023 now clears at a fraction of that through specialist GPU clouds, while current-generation Blackwell capacity holds a scarcity premium at the hyperscalers. The custom-silicon discount is the third lane: AWS pitches Trainium at 30–40% better price-performance than comparable GPU instances precisely because the chips carry no merchant margin. For steady, predictable inference at volume, that discount compounds every month of a contract's life.

Hyperscaler Custom ASICs and the New Vendor Lock-In

Custom silicon has crossed from science project to procurement strategy: all four of the largest clouds now field their own accelerators, and the 44.6% shipment growth projected for 2026 says the strategy is compounding. The build-or-buy calculus is brutally scale-dependent. A hyperscaler amortising a design across millions of servers strips out the merchant margin and tunes the chip to its own workloads; everyone below that scale inverts the maths, because a merchant GPU's premium buys a mature ecosystem and someone else's maintenance burden.

Behind most of these chips stand two companies few buyers ever transact with. Broadcom designs and implements the silicon for Google's TPU, Meta's MTIA and OpenAI's in-house accelerator, holds the majority of the AI-ASIC market, and in June 2026 unveiled a platform backed by Apollo and Blackstone to fund more than 20 gigawatts of custom AI compute through 2028 for frontier labs including Anthropic and OpenAI. Marvell, its main rival, builds for Amazon and Microsoft and reported fiscal-2026 revenue of US$8.2 billion, up 42%. The enablers matter to buyers for one reason: they reveal that every custom chip, like every merchant GPU, ends up as TSMC silicon wrapped in the same scarce high-bandwidth memory.

Deployment, not announcement, is now the differentiator. Google trains and serves Gemini on TPUs and rents Ironwood externally, and Anthropic has contracted for up to a million TPUs in a deal bringing well over a gigawatt of capacity online in 2026. Amazon's Project Rainier cluster runs Anthropic workloads across hundreds of thousands of Trainium2 chips, with Trainium3 quadrupling per-server compute, and Bedrock uses the same silicon to price hosted inference down. Microsoft's Maia 200 reached volume in January 2026 at roughly 10 PFLOPS per 750-watt chip — roughly six months later than first planned, with a Maia 300 successor targeted for a 2027 ramp, a reminder that first-party silicon is hard even with effectively unlimited budget. Meta's MTIA absorbs recommendation and inference load measured in NVIDIA orders never placed.

Does Custom Silicon Reduce Vendor Lock-In — or Simply Relocate It?

It relocates it, and sophisticated buyers should price the relocation. Escaping NVIDIA's software moat by adopting Trainium or TPU trades a portable dependency for a captive one: CUDA code moves between any cloud and any colocation hall, while a workload tuned for Trainium runs in exactly one company's data centres, at whatever that company prices it next contract cycle. The discount is real and the lock-in is real, and they are the same fact viewed from different ends of the contract.

The working posture for an enterprise is a portfolio, not a pledge. Keep the portable core on merchant silicon, place the highest-volume, most stable inference workloads where the custom-silicon discount is deepest, and maintain enough framework-level abstraction — PyTorch, JAX, managed inference APIs — that the threat of moving remains credible. Vendor diversity is not an ideology. It is the only negotiating instrument that works on both NVIDIA and the clouds simultaneously.

Singapore and Southeast Asia: Compute at the Edge of the Grid

In Southeast Asia the binding constraint is not chip allocation but electricity, and the region has quietly organised itself around that fact. Singapore operates on the order of 1.4 gigawatts of data-centre capacity and lifted its moratorium into a managed regime: the Green Data Centre Roadmap frees at least 300 megawatts of new capacity, with more available to operators that bring their own green energy, in exchange for hard efficiency targets. Every megawatt is conditional, which changes what gets built — high-density, liquid-cooled AI halls clear the bar; sprawling legacy designs do not.

The overflow crosses two borders. Johor has become the region's training annex, with a multi-gigawatt pipeline across Sedenak and the Iskandar corridor — including GPU campuses built explicitly around NVIDIA rack systems — and the Johor–Singapore Special Economic Zone formalising the pairing. Batam absorbs a second tranche via the Nongsa corridor. The operating pattern that is emerging: train where land and power are cheap, across the causeway or the strait; serve latency-sensitive inference from Singapore, where the subsea cables land and the regulated customers sit.

Singapore's second role in this market is upstream and underpriced in most strategy decks. The country already accounts for a meaningful share of global semiconductor output, and it is becoming a node in the memory chain that gates every HBM-based accelerator in this report: Micron is standing up advanced HBM packaging capacity in Singapore, its first such facility in the country, alongside a deep assembly-and-test ecosystem. A region that hosts HBM packaging, wafer fabs and AI data centres is no longer just a customer of the AI build-out. It is inside the supply chain that constrains it.

Where Should an APAC Procurement Team Place Its Accelerator Bets?

Cloud-first evaluation, portfolio commitment, power as a first-class specification. Every accelerator that matters can be evaluated from Singapore without importing a single card — AWS, Google Cloud and Azure all operate local regions, with each provider's newest silicon subject to regional rollout. The discipline that separates good programmes from expensive ones:

• Define the workload before the shortlist. Training from scratch, fine-tuning and high-volume inference point at different silicon; most enterprises are inference-heavy and should weight cost per token accordingly.
• Anchor on merchant silicon, price the alternative. Keep the portable core on NVIDIA or AMD, and carry a live TPU or Trainium quote into every renewal negotiation.
• Pilot one custom-silicon lane. Move a single high-volume, stable inference workload to a hyperscaler ASIC and measure the discount on your own traffic, not the vendor's benchmark.
• Treat power and residency as specifications. A 130 kW rack needs a hall that can cool it, and a regulated workload needs silicon available in an in-country region; both eliminate options faster than benchmarks do.
• Contract for allocation, not just price. Lead times on current-generation parts are quoted in quarters; a cheaper chip you cannot obtain is not an option, it is a delay.

The Close: Two Bottlenecks, No Solutions on the Table

Set aside the architecture war and two facts remain, neither of which any vendor on these pages can fix alone. Every flagship HBM accelerator this report names — Rubin, MI450, Ironwood, Trainium3, Maia, Sohu — is fabricated at TSMC and wrapped in high-bandwidth memory from the same three suppliers, then routed through advanced packaging capacity that remains effectively sold out through 2026. A dozen brands, one chokepoint. The diversification buyers are celebrating is real at the price sheet and narrows to almost nothing at the wafer.

The second bottleneck is the grid, and it is the one Southeast Asian buyers will feel first. Broadcom's financing platform alone contemplates more than 20 gigawatts of custom compute by 2028; Singapore's carefully rationed allocation for new data-centre capacity is 300 megawatts. At Blackwell densities of roughly 120–130 kW per rack, that entire national allocation — before cooling overhead — would energise on the order of 2,300 NVL72 racks.