- Foundry revenue is compared with foundry revenue. IDM revenue includes products, memory or other businesses and is not directly comparable.
- Exact 300 mm wafer starts, yields, HBM allocation and package capacity are usually confidential. Ranges and confidence labels are used where public data is incomplete.
- This guide is procurement research, not an investment recommendation or a guarantee of supply. Confirm any commercial assumption in a supplier quotation and capacity agreement.
Executive Summary and Key Takeaways
TSMC ranked first in the 2025 pure-play foundry market, while Samsung Foundry, SMIC, UMC and GlobalFoundries formed the next revenue tier. The 2025 top-10 foundry market was about US$169.5 billion according to TrendForce; TSMC accounted for roughly 70% of that market. The concentration is much higher at advanced logic nodes than across all foundry capacity.
WSTS forecasts global semiconductor sales of about US$1.51 trillion in 2026, with the forecast increase concentrated in memory and logic. That is a market-sales forecast, not a forecast of wafer availability or procurement prices.
| Buyer question | 2025 actual or public baseline | 2026 buying implication | Confidence |
|---|---|---|---|
| How large is the market? | US$795.6B global sales in 2025; WSTS forecast US$1.51T in 2026 | Plan for demand volatility; do not extrapolate market growth into guaranteed allocation | High |
| Who is the foundry revenue leader? | TSMC: about US$122.5B and 69.9% of the 2025 top-10 foundry market | Strongest ecosystem and scale; concentration and booking risk remain | High |
| What is the global 300 mm baseline? | About 9.0M wafers per month in a LambdaFin industry compilation | Use as a market order-of-magnitude only; supplier capacity is not interchangeable | Medium |
| Where is 2 nm? | TSMC and Samsung disclosed 2 nm ramps; public customer allocation is limited | Ask for node-specific PDK, yield, package and committed slot evidence | Medium |
| Who supplies HBM? | SK hynix, Samsung and Micron are the relevant memory IDMs | HBM4 timing depends on stack qualification and package integration, not launch claims | Medium-high |
Semiconductor Industry Snapshot 2026 and Why Rankings Matter
The 2026 semiconductor forecast describes demand, while procurement depends on usable capacity, packaging, qualification and commercial allocation. The source article on Semiconductor Wafer Starts 2026 estimates global 300 mm capacity at about 9.0M wafers per month, split across logic, DRAM, NAND, analog/power/RF and other categories. The estimate is useful for scale but should not be read as a contractual capacity number.
An integrated device manufacturer (IDM) designs and fabricates its own products, often including memory, analog, power or microcontrollers. A pure-play foundry primarily manufactures designs owned by other companies. Some companies operate both models. Fabless companies such as NVIDIA, AMD, Broadcom and Qualcomm are important demand sources but are not included as manufacturers in the ranking.
A wafer shortage may permit a mature-node redesign; a shortage of HBM or advanced packaging can delay the complete AI system. Track wafers, packaging, assembly/test, memory, power devices and export exposure as one bill of materials.
Rankings are decision aids, not quality awards: revenue does not measure yield, service, geographic diversity, change control or whether a smaller Singapore buyer can secure a slot.
Singapore Market Landscape
Singapore is an important semiconductor manufacturing, equipment and logistics base, but most Singapore buyers are purchasing into a global supply chain rather than from a single local fab. EDB states that Singapore contributes about 10% of global semiconductor output, about 5% of global wafer-fabrication capacity and about 20% of global semiconductor-equipment production.
That position supports regional distribution, equipment service and manufacturing partnerships, but does not remove exposure to overseas fabs, suppliers or shipping lanes.
For AI data-centre and regulated-industry buyers, the Singapore overlay is practical:
- IMDA and GovTech: map AI, cloud, data classification and public-sector security requirements before selecting a chip, cloud host or system integrator. IMDA's AI Verify and Model AI Governance Framework are useful governance references, not semiconductor quality certificates.
- MAS: financial institutions should map critical-system availability, recovery, incident notification and third-party oversight expectations to the semiconductor and infrastructure dependencies supporting those systems.
- PDPC: the PDPA remains relevant when design, telemetry, customer or employee data moves through overseas suppliers, cloud environments, test labs or support systems. The Transfer Limitation Obligation requires comparable protection for personal data transferred outside Singapore.
- Talent and packaging: Singapore has deep manufacturing and equipment capabilities, but advanced packaging, chiplet integration, thermal engineering and specialist design talent may still require regional partners and long qualification cycles.
Evaluation Framework for Enterprise Buyers
A semiconductor supplier scorecard should weight usable supply and qualification evidence at least as heavily as revenue or process-node marketing. Use the following seven dimensions:
| Criterion | What to verify | Typical failure mode |
|---|---|---|
| Financial resilience | 2025 audited revenue, segment mix, capex, debt and customer concentration | Comparing IDM total revenue with foundry revenue |
| Capacity and allocation | Site/node starts, reserved slot, ramp, cycle time and allocation rules | Confusing installed tools with qualified capacity |
| Process readiness | PDK, design rules, IP, yield, reliability data and change notices | Choosing the smallest node before design and package costs are known |
| HBM and packaging | Memory qualification, stack, interposer, substrate, assembly/test and thermal limits | Securing wafers without package or HBM allocation |
| Power-semiconductor fit | SiC/GaN voltage, frequency, package, grade, lifecycle and reference designs | Using a lab-rated device in a production thermal envelope |
| Geopolitical and export risk | Fab/package sites, ownership, US/EU controls, licences, end use and alternates | Assuming a non-US supplier is outside US controls |
| Dual-source feasibility | Second PDK, package, test, firmware, qualification budget and lead time | Calling two distributors a dual source |
Questions to put in the RFQ
- Which fab and package site will supply the part, and what monthly quantity, allocation period, lead time and recovery plan are committed?
- What evidence supports the node, yield, reliability grade, HBM stack and package configuration?
- Which export controls, change notices, warranty, business-continuity, liability and exit terms apply?
Vendor Landscape: 2025 Foundry Revenue Ranking
TSMC had the largest 2025 foundry revenue by a wide margin, but this is not a universal supplier ranking. TrendForce puts the top 10 at about US$169.5B; figures below are rounded and limited to foundry revenue.
| Rank | Foundry | 2025 revenue | Top-10 share | Enterprise fit and limitation |
|---|---|---|---|---|
| 1 | TSMC | ~US$122.5B | ~69.9% | Advanced logic, mature nodes and packaging ecosystem; Taiwan concentration, booking pressure and pricing power |
| 2 | Samsung Foundry | ~US$12.6B | ~7.2% | Advanced GAA roadmap and IDM memory relationship; external foundry scale and yield comparability require qualification |
| 3 | SMIC | ~US$9.3B | ~5.3% | China domestic supply and broad mature-node capability; export controls and advanced-node tool access constrain options |
| 4 | UMC | ~US$7.6B | ~4.4% | Established mature-node, automotive and industrial supply; not a substitute for 2 nm or 3 nm logic |
| 5 | GlobalFoundries | ~US$6.8B | ~3.9% | RF, FD-SOI, automotive, aerospace and industrial platforms; limited advanced-logic path |
| 6 | HuaHong Group | ~US$4.5B | ~2.6% | Power, analog, MCU and China localisation; site and entity scope must be checked for each programme |
| 7-10 | Tower, Vanguard, Powerchip and other foundries | Not consistently disclosed in one comparable public table | Remainder | Specialty, analog, RF, display-driver and mature-node options; evaluate by process and site, not league-table position |
Ranking note: the figures come from TrendForce's 2025 foundry research as reported in its March 2026 release. They should not be mixed with Samsung Electronics, SK hynix, Micron or Intel total-company revenue.
Capacity, Process Nodes and Technology Comparison
No reliable public league table covers qualified 300 mm capacity across every supplier; this table ranks public evidence rather than inventing precision.
| Supplier | Public capacity signal | Node or platform position | Capacity risk for a buyer |
|---|---|---|---|
| TSMC | >17M annual 12-inch-equivalent wafers in 2025 | N2 ramp; N3/N4/N5 volume; advanced packaging | Concentration, allocation and package bottlenecks |
| Samsung | Large 300 mm memory/foundry network; no comparable public foundry total | 3 nm GAA and 2 nm roadmap | Separate business priorities and qualification uncertainty |
| Intel | Large US, Ireland and Israel network; external pool still developing | 18A ramp; 14A development; advanced packaging | Customer base, yield ramp and ecosystem maturity |
| UMC / GlobalFoundries | Multi-site mature-node capacity; free capacity is quote-driven | 12-40 nm, RF, FD-SOI, analog, auto and industrial | Cycle exposure and uneven node utilisation |
| SMIC / HuaHong | Large China-based mature-node networks; site totals not comparable | SMIC 7 nm-class path; broad mature nodes | Export controls, policy and cross-border support |
Technology fit by application
| Requirement | Shortlist | What the buyer must validate |
|---|---|---|
| AI accelerator logic at 2-5 nm | TSMC; Samsung as a second process path; Intel 18A for selected programmes | PDK maturity, die size, yield, CoWoS or equivalent package, HBM and substrate allocation |
| HBM and AI memory | SK hynix, Samsung and Micron | HBM3E/HBM4 stack, qualification with the target accelerator, thermal envelope and allocation |
| Automotive and industrial mixed-signal | GlobalFoundries, UMC, Samsung, TI, Infineon, ST, NXP and onsemi | Automotive grade, PPAP or equivalent, lifecycle, change control and regional supply |
| SiC power devices | Infineon, onsemi, STMicroelectronics and Wolfspeed | Voltage class, wafer quality, package, switching loss, field reliability and capacity ramp |
| GaN power devices | Infineon, TI, Navitas and specialist suppliers, subject to application fit | Frequency, gate drive, qualification, thermal design, system reference and second source |
Major IDMs and Specialty Semiconductor Suppliers
IDMs matter because many enterprise products need memory, analog, power, microcontrollers and sensors alongside foundry-produced logic. Their 2025 revenue is not directly comparable to the foundry ranking, so use this as a capability shortlist.
| Supplier | Primary buying case | Strength | Limitation to price and qualify |
|---|---|---|---|
| Samsung Electronics | Memory, HBM, logic and foundry | One relationship can cover several layers | Business-unit priorities and qualification remain separate |
| SK hynix | HBM, DRAM and enterprise SSD | KRW97.1T FY2025 revenue; HBM a major driver | Memory-cycle exposure and concentrated allocation |
| Micron | HBM, DRAM, NAND and Singapore assembly | US$37.4B FY2025 revenue; expanding HBM | Fiscal-year basis, ramp and qualification differ |
| Intel | CPU, edge, packaging and external foundry | 18A entered high-volume production in 2025 | External customer base remains limited |
| TI | Analog, power and embedded processing | Broad portfolio and long lifecycles | Not a 2 nm or HBM supplier; allocation varies by device |
| Infineon, ST, onsemi | Automotive, industrial, power, SiC and GaN | Power portfolios and automotive qualification | Ramp schedules and device-specific second-source limits |
| NXP | Automotive, industrial, edge and secure embedded | System-level automotive and industrial portfolio | Not a substitute for AI logic, HBM or every SiC design |
| Wolfspeed | SiC materials and power devices | High-voltage power-conversion focus | Review capacity execution, finances and qualification |
Pricing Models and Total Cost of Ownership
Wafer price is only one line in semiconductor TCO; the economic unit is a qualified part delivered in volume. Ask suppliers to separate:
- wafer, mask/reticle, NRE, engineering-wafer and prototype charges;
- assembly, test, burn-in, substrate, interposer, memory stack and thermal materials;
- qualification, reliability, security, capacity reservation, minimum order and expedite terms; and
- yield loss, logistics, duty, inventory, currency and redesign cost after a disruption.
Advanced AI parts can win on system TCO if they reduce accelerators, memory, racks or cooling. Mature-node power devices may cost less per die but more at system level through energy and cooling. Model board, rack and three-year product cost.
For a power-semiconductor shortlist, compare efficiency at the actual load curve, frequency, temperature, duty cycle, fault profile and service life, then price the complete power stage and second source.
Compliance, Security and Supply-Chain Risk
Semiconductor procurement in Singapore is governed by a combination of product, data, financial-sector, export-control and contract requirements rather than one semiconductor-specific law.
Export controls and geopolitical exposure
The US CHIPS Act, EU Chips Act, US export controls and China localisation policies influence where fabs are built, which tools and designs can move, and who can receive advanced AI components. Put the analysis at part, site, technology and end-use level. A company headquartered in one country can operate a fab, package a die or use controlled EDA and equipment from several others.
Security and governance evidence
- Request ISO/IEC 27001 scope and audit evidence for design files, portals, PDKs and support; ask about access control, secure development and incident notification.
- Use ISO/IEC 42001 and NIST AI RMF for AI governance, and IMDA/AI Verify plus PDPC requirements for relevant Singapore projects. These do not prove wafer quality.
- MAS-regulated buyers should map critical systems, third parties, recovery objectives and incident reporting to MAS Technology Risk Management requirements.
- Public-sector buyers should confirm GovTech and agency-specific security, hosting, data-classification and procurement requirements.
Contract minimum: make location, sub-tier suppliers, export-control status, product-change notice, business continuity, audit rights, allocation priority and exit assistance contractual. A certificate without scope and remedy is weak evidence.
Implementation Roadmap and Common Pitfalls
Capacity planning should begin when the architecture and application forecast are still changeable, not when a purchase order is due.
- 0-3 months: define performance, power, lifecycle, geography, compliance and demand scenarios; separate advanced logic, memory, power and mature-node parts.
- 3-9 months: obtain PDK and IP access, run supplier RFQs, model package and test constraints, and negotiate a non-binding capacity plan with clear assumptions.
- 9-18 months: tape out or freeze the design, reserve wafers and package capacity, qualify a second source for the highest-risk components, and complete export-control review.
- 18-36 months: run reliability and field pilots, validate yield and supply continuity, execute a controlled ramp, and keep a redesign or substitution path alive.
Common failures include treating a press release as capacity, securing wafers without packaging, choosing 2 nm for prestige, underestimating substrate/HBM allocation, accepting a distributor as a second source, and leaving redesign ownership undefined.
Future Outlook: 2026-2030
Through 2030, the semiconductor supply chain is likely to become more geographically distributed but not less concentrated at the newest logic nodes.
- 2 nm and 1.4 nm: monitor TSMC, Samsung and Intel; early availability depends on yield, PDK, packaging and allocation, not node name alone.
- HBM4 and HBM4E: capacity will expand, but stack qualification, thermal limits and packaging can bottleneck complete AI systems.
- SiC and GaN: demand will grow across vehicles, industrial power and AI datacentres; device choice remains application-specific.
- Geopolitics and Singapore: CHIPS Act/EU Chips Act incentives may diversify supply while adding compliance and non-interchangeability. Evaluate Singapore as part of a network, not a guarantee of local advanced components.
Frequently Asked Questions
Which semiconductor foundry has the largest revenue in 2025?
TSMC ranked first in TrendForce's 2025 foundry revenue ranking, with about US$122.5B and roughly 70% of the top-10 foundry market. That is foundry revenue, not total semiconductor revenue, and it does not mean that unallocated capacity is available to a new buyer.
Which foundry is the safest default for an AI accelerator?
TSMC is the default benchmark for advanced logic ecosystem maturity and scale, but “default” does not mean guaranteed capacity or lowest TCO. Samsung and, for selected programmes, Intel should be evaluated when geographic diversification, government supply-chain requirements or a specific process/package fit matters.
What does HBM4 availability in 2026 actually mean?
It means a qualified memory stack is available in the exact package and allocation required by the accelerator. Ask for a qualification matrix, stack configuration, sample dates, volume ramp, thermal data and committed monthly allocation.
Can mature nodes still be tight?
Yes. Mature nodes support power-management ICs, analog, display drivers, automotive MCUs, sensors and RF. AI data-centre growth can increase demand for those supporting devices even when the AI logic is fabricated at 3 nm or 5 nm.
Should a Singapore buyer prefer a local supplier?
Local presence is useful for service, logistics, engineering and accountability, but the fab and package may be elsewhere. Score the actual manufacturing network, not the sales-office address.
How do I compare TSMC vs Samsung for a 2 nm design?
Compare PDK maturity, IP availability, design cost, yield evidence, package route, HBM and substrate access, commercial allocation, export risk, geographic requirements and the cost of a second design flow. Do not compare node names alone.
Are SiC and GaN interchangeable?
No. SiC is commonly considered for higher-voltage and higher-power applications; GaN can be attractive for high-frequency power conversion in suitable voltage ranges. The system topology, thermal design, gate drive and reliability requirements decide the choice.
Do export controls affect a mature-node purchase?
They can affect equipment, EDA, design files, end use, end user, re-export and support even when the device itself is not an advanced AI chip. Ask the supplier to map the complete transaction and provide a contingency route.
What is the right dual-sourcing strategy?
Dual-source the highest business-impact bottleneck first. That is often HBM, advanced packaging, a power device or a mature-node controller rather than the main logic die. Fund the alternate design and qualification work before the disruption, not after it.
Final Recommendations and Procurement Checklist
The right 2026 semiconductor portfolio is one that meets the product's performance target while preserving a credible route around capacity, package, geopolitical and qualification risk.
Start with the Semiconductor Company Directory, browse AI accelerator and AI-computing providers, and use the RFQ and procurement templates to turn this framework into a supplier brief. For power devices, use the Power Semiconductor category where available, then confirm every capability directly with the supplier.
Sources and Method
Method: 2025 disclosures and market datasets plus 2026 forecasts available at publication. Capacity is labelled disclosed, estimated or not comparable; public capacity is not free capacity.
- LambdaFin; TrendForce; and TSMC 2025 Annual Report.
- WSTS; SIA; Intel; Samsung; SK hynix; and Micron.
- Singapore EDB; IMDA; PDPC; and MAS.
- ISO 42001; ISO 27001; NIST AI RMF; US CHIPS; EU Chips Act; and BIS.